1. Field of the Invention
This invention is related to the field of computer systems and, more particularly, to memory controllers in computer systems.
2. Description of the Related Art
Memory controllers are included in computer systems to manage access to memory. Typically, the memory includes some form of dynamic random access memory (DRAM). Varieties of DRAM include asynchronous DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Rambus DRAM (RDRAM), etc. Some computer systems may include a single memory comprising one or more DRAMs and a single memory controller to control access to the memory. Other systems, referred to as distributed memory computer systems, may include multiple memories (each comprising one or more DRAMs) separately accessible using respective memory controllers.
Typically, a given memory may require a minimum number of bytes to be written when a write is performed to the memory, which will be referred to as the xe2x80x9cwrite widthxe2x80x9d. The write width may, for example, be the width of one data transfer to/from the memory. Alternatively, the write width may be a portion of the data transfer or multiple data transfers.
If a write request is received by the memory controller, and the write request updates a number of bytes less than the write width, the memory controller may perform a read-modify-write operation to complete the write request. The memory controller typically includes a data buffer into which the write data is stored (using a first port on the data buffer). The memory controller then reads at least a write-width of data from the memory, and provides that data directly to the data buffer using a second port on the buffer. The read data is merged with the write data in the buffer (thus modifying the read data with the write data), and written back to memory. The read-modify-write is entirely local to the memory controller.
An apparatus is contemplated, including a router and a memory controller. The router is configured to route a write request and write data to the memory controller. The memory controller is coupled to receive the write request and the write data. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, the memory controller is configured to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The memory controller is configured to return the first data to the router as a read response. The router is configured to return the first data to the memory controller.
A memory controller is contemplated, comprising a request queue coupled to receive a write request, a data buffer coupled to receive write data corresponding to the write request, and a control circuit coupled to the request queue and the data buffer. The control circuit is configured, if the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The control circuit is further configured to transmit the first data as a read response. The data buffer is coupled to receive the first data returned to the memory controller as a read response, and the control circuit is configured to merge the first data and the write data.
A method is also contemplated. A write request and write data are received in a memory controller. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, first data is read from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The first data is transmitted from the memory controller as a read response, and is received in the memory controller.